The advance and development of the data processing industry has seen efforts toward increasing the speed and reducing the size of the component parts of data processing systems together with an integration of the processor systems themselves, thereby realizing sophisticated multiprocessor networks. As the processors within the network interact with one another in performing the respective tasks for which they have been programmed, interprocessor interrupts are employed when a processor requires the services of another processor. For this purpose, it has been a common practice to assign respective interrupt lines for each of the processors of the system and to interconnect these lines individually to every respective processor, usually in accordance with some form of priority scheme for handling the interrupts. Unfortunately, as the number of processors per network increases, the corresponding number of interrupt lines required makes this approach impractical if not almost impossible to implement.
In an effort to circumvent the wiring problem associated with the above approach, there has been proposed a scheme whereby the interrupt lines are encoded and a processor for whom an interrupt is intended is selectively addressed. At the destination processor, the interrupts are sequentially stored in a first-in, first-out register (FIFO), and the destination processor handles the interrupts on a first-come, first-served basis. Now, although this scheme offers a reduction in the number of interrupt lines, it also has its own drawbacks. For one thing, additional hardward is required for the destination processor to acknowledge the handling of an incoming interrupt. Also, the interrupts cannot be prioritized, since the destination processor handles each request in the order in which it is received.
A major shortcoming of each of the above schemes is their inability to provide a status of all interrupts to every processor on a continual basis. In modern sophisticated multiprocessor environments, this requirement is extremely important, as it not only permits tasks to be handled on a priority basis, but enables the time efficiency of system operation to be maximized.
An additional shortcoming of employing the above schemes in a multiprocessor environment is the requirement that a processor which uses interrupts to communicate with another processor must use a different mechanism if it is to interrupt itself; this lack of uniformity introduces additional complexity into the software.